1. Field of the Invention
The present invention relates to the manufacture and testing of integrated circuits; and more particularly to circuits to test integrated circuits such as EEPROMs or FLASH EPROMs for engineering and production purposes.
2. Description of Related Art
In the manufacture of integrated circuits, testing for both engineering and production purposes is critical. Thus, most integrated circuits incorporate test circuitry on the chip to facilitate the testing processes. The ability to test a large number of devices at one time is particularly important for production purposes, where the testing step is incorporated into the method for manufacturing the integrated circuit. In production testing systems for "gangs" of integrated circuits, the amount of data which must be monitored by a processor controlling the testing can be quite large. This slows down the testing processes, and limits the amount of information which can be processed during the testing mode.
Testing is of significant importance in the non-volatile memory device field. For instance, the memory devices must be tested for endurance, and qualified according to read and write speed specifications during manufacturing. Also, the endurance and read and write speed parameters of the circuit are important for engineering purposes during the design of a product.
Non-volatile memory design based on integrated circuit technology represents an expanding field. One popular class of non-volatile memory cell is known as the erasable-programmable read only memory (EPROM). Two popular EPROM designs are distinguished in the manner in which isolation of the memory cells is carried out. The first is referred to as the EEPROM. A second member of this class is known as the FLASH EPROM which uses a higher density format.
Both the FLASH EPROM and EEPROM technologies are based on a memory cell which consists of a source, channel, and drain with a floating gate over the channel and a control gate isolated from the floating gate. The act of programming the cell involves charging the floating gate with electrons which causes the turn-on threshold of the memory cell to increase. Thus, when programmed the cell will not turn on, that is it will remain non-conductive, when addressed with a read potential applied to its control gate. The act of erasing the cell involves removing electrons from the floating gate to lower the threshold. With the lower threshold, the cell will turn on to a conductive state when addressed with a read potential to the control gate.
The regular EEPROM designs use either a two transistor cell structure which includes a pass gate that isolates the memory cell from the bitline or a split-gate structure which behaves like two transistors in series to isolate un-selected cells, so that unselected memory cells do not contribute leakage current to the bitline. The higher density FLASH EPROM cell does not use the isolation transistor or split-gate.
Further, commercial FLASH EPROM designs include circuitry for verifying the success of programming and erasing steps. See, for instance, U.S. Pat. No. 4,875,118, entitled VOLTAGE MARGINING CIRCUIT FOR FLASH EPROM, invented by Jungroth.
Also, commercial devices incorporate automatic program and erase modes which can be used for testing the operation of the non-volatile design.
In order to meet specific quality requirements for non-volatile memory devices like FLASH EPROMs and EEPROMs, program and erase cycling is required to screen out devices which have low endurance (i.e., suffer "infant mortality"). To simplify the hardware requirements for the testing and reduce the cycle time, gang cycling is required in the production environment. Thus, it would be desirable to provide an automatic program and erase mode with some intelligence to facilitate gang cycling. For engineering, it is also important to have a mode that will record the status of the device during cycling to indicate the endurance of the specific device.